GBA Tests: Difference between revisions

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undoSczther (talk | contribs)
175 edits
VisualWikitext
Sczther (talk | contribs)
175 edits
Added No$GBA results
Sczther (talk | contribs)
175 edits
Added MiSTer_GBA results
Line 34: Line 34:
|-
|-
![[MiSTer|MiSTer_GBA]]
![[MiSTer|MiSTer_GBA]]
|v240409
|v250621
|-
|-
![[FPGA|Analogue Pocket]]
![[FPGA|Analogue Pocket]]
Line 115: Line 115:
|SIO register R/W tests</abbr>
|SIO register R/W tests</abbr>
|90
|90
|{{Fail}} (25) ||{{Fail}} (18) ||{{Fail}} (28) ||{{Fail}} (25) ||{{Fail}} (61) ||{{Fail}} (34) ||{{Fail}} (36) ||{{Fail}} (13) ||{{Fail}} (25)<sup>[[#star3|***]]</sup> ||Not Tested  
|{{Fail}} (25) ||{{Fail}} (18) ||{{Fail}} (28) ||{{Fail}} (25) ||{{Fail}} (61) ||{{Fail}} (34) ||{{Fail}} (36) ||{{Fail}} (13) ||{{Fail}} (27) ||Not Tested  
|-
|-
!12
!12
|<abbr title="needs link cable plugged in for half the tests">SIO timing tests</abbr>
|<abbr title="needs link cable plugged in for half the tests">SIO timing tests</abbr>
|8
|8
|{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0)<sup>[[#star3|***]]</sup> ||Not Tested  
|{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||{{Fail}} (0) ||Not Tested  
|-
|-
!13
!13
|{{Yellow}}<abbr title="needs to be run as a first test after boot">Misc. edge case tests</abbr><sup>[[#star4|****]]</sup>
|{{Yellow}}<abbr title="needs to be run as a first test after boot">Misc. edge case tests</abbr><sup>[[#star3|***]]</sup>
|10
|10
|{{Fail}} (8) ||{{Fail}} (8) ||{{Fail}} (8) ||{{Fail}} (4) ||{{Fail}} (8) ||{{Fail}} (7)<sup>[[#star2|**]]</sup> ||{{Fail}} (6) ||{{Fail}} (8) ||{{Fail}} (6)<sup>[[#star2|**]]</sup> ||{{Pass}}<sup>[[#star1|*]]</sup>
|{{Fail}} (8) ||{{Fail}} (8) ||{{Fail}} (8) ||{{Fail}} (4) ||{{Fail}} (8) ||{{Fail}} (7)<sup>[[#star2|**]]</sup> ||{{Fail}} (6) ||{{Fail}} (8) ||{{Fail}} (6)<sup>[[#star2|**]]</sup> ||{{Pass}}<sup>[[#star1|*]]</sup>
Line 136: Line 136:
<span id="star1"><nowiki>*</nowiki>    tested on r83</span><br>
<span id="star1"><nowiki>*</nowiki>    tested on r83</span><br>
<span id="star2"><nowiki>**</nowiki>  inconsistent results, showcasing highest value seen</span><br>
<span id="star2"><nowiki>**</nowiki>  inconsistent results, showcasing highest value seen</span><br>
<span id="star3"><nowiki>***</nowiki>  tested with GBA2P v220813</span><br>
<span id="star3"><nowiki>***</nowiki> two of the tests are acting a bit weird and need to be checked, using a flashcart they don't pass</span>
<span id="star4"><nowiki>****</nowiki> two of the tests are acting a bit weird and need to be checked, using a flashcart they don't pass</span>


===AGS Aging Cartridge===
===AGS Aging Cartridge===
Line 291: Line 290:
|DMA_Mode_Change
|DMA_Mode_Change
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 45 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 45 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!02
!02
|DMA_pause_timing_end_1
|DMA_pause_timing_end_1
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 216 ||{{Fail}} test 6 ||{{Fail}} test 243 ||{{Fail}} test 12 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 216 ||{{Fail}} test 6 ||{{Fail}} test 243 ||{{Fail}} test 12 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!03
!03
|DMA_pause_timing_end_2
|DMA_pause_timing_end_2
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 217 ||{{Fail}} test 5 ||{{Fail}} test 244 ||{{Pass}} ||{{Fail}} test 1 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 217 ||{{Fail}} test 5 ||{{Fail}} test 244 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 10 ||Not Tested
|-
|-
!04
!04
|DMA_pause_timing_end_3
|DMA_pause_timing_end_3
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 216 ||{{Fail}} test 6 ||{{Fail}} test 243 ||{{Fail}} test 12 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 216 ||{{Fail}} test 6 ||{{Fail}} test 243 ||{{Fail}} test 12 ||{{Pass}} ||{{Fail}} test 11 ||Not Tested
|-
|-
!05
!05
|DMA_pause_timing_end_4
|DMA_pause_timing_end_4
|
|
|Not Tested ||{{Fail}} test 14 ||{{Pass}} ||{{Fail}} test 217 ||{{Fail}} test 5 ||{{Fail}} test 244 ||{{Fail}} test 12 ||{{Fail}} test 1 ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 14 ||{{Pass}} ||{{Fail}} test 217 ||{{Fail}} test 5 ||{{Fail}} test 244 ||{{Fail}} test 12 ||{{Fail}} test 1 ||{{Fail}} test 8 ||Not Tested
|-
|-
!06
!06
|DMA_pause_timing_mid_1
|DMA_pause_timing_mid_1
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 217 ||{{Fail}} test 6 ||{{Fail}} test 244 ||{{Fail}} test 12 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 217 ||{{Fail}} test 6 ||{{Fail}} test 244 ||{{Fail}} test 12 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!07
!07
|DMA_pause_timing_mid_2
|DMA_pause_timing_mid_2
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 216 ||{{Fail}} test 5 ||{{Fail}} test 245 ||{{Fail}} test 12 ||{{Fail}} test 1 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 216 ||{{Fail}} test 5 ||{{Fail}} test 245 ||{{Fail}} test 12 ||{{Fail}} test 1 ||{{Fail}} test 8 ||Not Tested
|-
|-
!08
!08
|DMA_pause_timing_ROM_to_IWRAM
|DMA_pause_timing_ROM_to_IWRAM
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 113 ||{{Fail}} test 112 ||{{Fail}} test 117 ||{{Fail}} test 109 ||{{Fail}} test 9 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 113 ||{{Fail}} test 112 ||{{Fail}} test 117 ||{{Fail}} test 109 ||{{Fail}} test 9 ||{{Fail}} test 111 ||Not Tested
|-
|-
!09
!09
Line 348: Line 347:
|FIFO_3
|FIFO_3
|
|
|Not Tested ||{{Fail}} test 174 ||{{Pass}} ||{{Fail}} test 102 ||{{Fail}} test 111 ||{{Fail}} test 146 ||{{Fail}} test 121 ||{{Fail}} test 75 ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 174 ||{{Pass}} ||{{Fail}} test 102 ||{{Fail}} test 111 ||{{Fail}} test 146 ||{{Fail}} test 121 ||{{Fail}} test 75 ||{{Fail}} test 51 ||Not Tested
|-
|-
!04
!04
|FIFO_4
|FIFO_4
|
|
|Not Tested ||{{Fail}} test 124 ||{{Pass}} ||{{Fail}} test 95 ||{{Fail}} test 95 ||{{Fail}} test 95 ||{{Fail}} test 94 ||{{Fail}} test 45 ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 124 ||{{Pass}} ||{{Fail}} test 95 ||{{Fail}} test 95 ||{{Fail}} test 95 ||{{Fail}} test 94 ||{{Fail}} test 45 ||{{Fail}} test 95 ||Not Tested
|-
|-
!05
!05
|FIFO_5
|FIFO_5
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 59 ||{{Fail}} test 59 ||{{Fail}} test 59 ||{{Fail}} test 62 ||{{Fail}} test 54 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 59 ||{{Fail}} test 59 ||{{Fail}} test 59 ||{{Fail}} test 62 ||{{Fail}} test 54 ||{{Fail}} test 59 ||Not Tested
|-
|-
!06
!06
|FIFO_6
|FIFO_6
|
|
|Not Tested ||{{Fail}} test 118 ||{{Pass}} ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} test 117 ||{{Fail}} test 90 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 118 ||{{Pass}} ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} test 117 ||{{Fail}} test 90 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!colspan="13"|Interactions
!colspan="13"|Interactions
Line 370: Line 369:
|Halt_DMA_IRQ
|Halt_DMA_IRQ
|
|
|{{Pass}} ||{{Fail}} test 184 ||{{Pass}} ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 184 ||{{Pass}} ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||Not Tested
|-
|-
!02
!02
|Halt_DMA_IRQ_Read_OAM
|Halt_DMA_IRQ_Read_OAM
|
|
|{{Pass}} ||{{Fail}} test 184 ||{{Pass}} ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 56 ||{{Fail}} test 184 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 184 ||{{Pass}} ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 56 ||{{Fail}} test 184 ||{{Fail}} test 184 ||Not Tested
|-
|-
!03
!03
|Halt_IRQ
|Halt_IRQ
|
|
|{{Pass}} ||{{Fail}} test 184 ||{{Pass}} ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 94 ||{{Fail}} test 184 ||{{Fail}} test 184 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 184 ||{{Pass}} ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 94 ||{{Fail}} test 184 ||{{Fail}} test 184 ||{{Fail}} test 184 ||Not Tested
|-
|-
!04
!04
Line 390: Line 389:
|Internal_Cycle_DMA_IRQ_7
|Internal_Cycle_DMA_IRQ_7
|
|
|{{Pass}} ||{{Fail}} test 6 ||{{Pass}} ||{{Fail}} test 248 ||{{Fail}} test 4 ||{{Fail}} test 248 ||{{Fail}} test 6 ||{{Fail}} test 10 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 6 ||{{Pass}} ||{{Fail}} test 248 ||{{Fail}} test 4 ||{{Fail}} test 248 ||{{Fail}} test 6 ||{{Fail}} test 10 ||{{Fail}} test 6 ||Not Tested
|-
|-
!06
!06
|Internal_Cycle_DMA_IRQ_br
|Internal_Cycle_DMA_IRQ_br
|
|
|{{Pass}} ||{{Fail}} test 20 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 20 ||{{Fail}} test 20 ||{{Pass}} ||{{Fail}} test 76 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 20 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 20 ||{{Fail}} test 20 ||{{Pass}} ||{{Fail}} test 76 ||{{Fail}} test 24 ||Not Tested
|-
|-
!07
!07
|Internal_Cycle_DMA_IRQ_br1_IWRAM
|Internal_Cycle_DMA_IRQ_br1_IWRAM
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 90 ||{{Fail}} test 90 ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 90 ||{{Fail}} test 90 ||{{Fail}} test 36 ||Not Tested
|-
|-
!08
!08
|Internal_Cycle_DMA_IRQ_Br_pre
|Internal_Cycle_DMA_IRQ_Br_pre
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 28 ||{{Fail}} test 26 ||{{Pass}} ||{{Pass}}||{{Fail}} test 76 ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 28 ||{{Fail}} test 26 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 76 ||{{Pass}} ||Not Tested
|-
|-
!09
!09
|Internal_Cycle_DMA_IRQ_Br_pre_tim
|Internal_Cycle_DMA_IRQ_Br_pre_tim
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 32 ||{{Fail}} test 27 ||{{Fail}} test 255 ||{{Fail}} test 2 ||{{Fail}} test 1 ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 32 ||{{Fail}} test 27 ||{{Fail}} test 255 ||{{Fail}} test 2 ||{{Fail}} test 1 ||{{Fail}} test 25 ||Not Tested
|-
|-
!10
!10
|Internal_Cycle_DMA_IRQ_ldr_IWRAM
|Internal_Cycle_DMA_IRQ_ldr_IWRAM
|
|
|{{Pass}} ||{{Fail}} test 32 ||{{Pass}} ||{{Fail}} test 16 ||{{Fail}} test 20 ||{{Fail}} test 20 ||{{Fail}} test 32 ||{{Fail}} test 38 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 32 ||{{Pass}} ||{{Fail}} test 16 ||{{Fail}} test 20 ||{{Fail}} test 20 ||{{Fail}} test 32 ||{{Fail}} test 38 ||{{Fail}} test 28 ||Not Tested
|-
|-
!11
!11
|Internal_Cycle_DMA_IRQ_nop_IWRAM
|Internal_Cycle_DMA_IRQ_nop_IWRAM
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 36 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 94 ||{{Fail}} test 94 ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 36 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 94 ||{{Fail}} test 94 ||{{Pass}} ||Not Tested
|-
|-
!12
!12
|Internal_Cycle_DMA_IRQ_ST
|Internal_Cycle_DMA_IRQ_ST
|
|
|{{Pass}} ||{{Fail}} test 8 ||{{Pass}} ||{{Fail}} test 248 ||{{Fail}} test 4 ||{{Fail}} test 248 ||{{Pass}} ||{{Fail}} test 54 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 8 ||{{Pass}} ||{{Fail}} test 248 ||{{Fail}} test 4 ||{{Fail}} test 248 ||{{Pass}} ||{{Fail}} test 54 ||{{Fail}} test 6 ||Not Tested
|-
|-
!13
!13
|Internal_Cycle_DMA_IRQ_ST_p3
|Internal_Cycle_DMA_IRQ_ST_p3
|
|
|{{Pass}} ||{{Fail}} test 8 ||{{Pass}} ||{{Fail}} test 6 ||{{Fail}} test 6 ||{{Fail}} test 8 ||{{Pass}} ||{{Fail}} test 62 ||Not Tested ||Not Tested
|{{Pass}} ||{{Fail}} test 8 ||{{Pass}} ||{{Fail}} test 6 ||{{Fail}} test 6 ||{{Fail}} test 8 ||{{Pass}} ||{{Fail}} test 62 ||{{Pass}} ||Not Tested
|-
|-
!14
!14
Line 440: Line 439:
|Internal_Cycle_DMA_MUL_IRQ
|Internal_Cycle_DMA_MUL_IRQ
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 8 ||{{Fail}} test 14 ||{{Fail}} test 6 ||{{Fail}} test 134 ||{{Fail}} test 24 ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 8 ||{{Fail}} test 14 ||{{Fail}} test 6 ||{{Fail}} test 134 ||{{Fail}} test 24 ||{{Fail}} test 20 ||Not Tested
|-
|-
!16
!16
|Internal_Cycle_DMA_TIM_Br_pre
|Internal_Cycle_DMA_TIM_Br_pre
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 32 ||{{Fail}} test 27 ||{{Fail}} test 255 ||{{Fail}} test 2 ||{{Fail}} test 1 ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 32 ||{{Fail}} test 27 ||{{Fail}} test 255 ||{{Fail}} test 2 ||{{Fail}} test 1 ||{{Fail}} test 25 ||Not Tested
|-
|-
!colspan="13"|IRQ
!colspan="13"|IRQ
Line 452: Line 451:
|BL_1
|BL_1
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} (crash) ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} (crash) ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!02
!02
|BL_IRQ
|BL_IRQ
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 245 ||{{Fail}} test 240 ||{{Pass}} ||{{Fail}} test 245 ||{{Fail}} test 224 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 245 ||{{Fail}} test 240 ||{{Pass}} ||{{Fail}} test 245 ||{{Fail}} test 224 ||{{Fail}} test 250 ||Not Tested
|-
|-
!03
!03
|BL_IRQ_2
|BL_IRQ_2
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} (crash) ||{{Fail}} test 2 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} (crash) ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested
|-
|-
!04
!04
|BL_IRQ_3
|BL_IRQ_3
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||Not Tested
|-
|-
!05
!05
|BL_IRQ_R14
|BL_IRQ_R14
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||Not Tested
|-
|-
!06
!06
|Halt_PC
|Halt_PC
|
|
|{{Pass}} ||{{Fail}} test 212 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 184 ||{{Pass}}
|{{Pass}} ||{{Fail}} test 212 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 2 ||{{Pass}}
|-
|-
!07
!07
Line 517: Line 516:
|IRQ_sub_slow
|IRQ_sub_slow
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 229 ||{{Fail}} test 239 ||{{Pass}} ||{{Fail}} test 243 ||{{Fail}} test 224 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 229 ||{{Fail}} test 239 ||{{Pass}} ||{{Fail}} test 243 ||{{Fail}} test 224 ||{{Fail}} test 237 ||Not Tested
|-
|-
!15
!15
|IRQ_sub_2
|IRQ_sub_2
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 28 ||{{Fail}} test 218 ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} test 216 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 28 ||{{Fail}} test 218 ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} test 216 ||{{Fail}} test 220 ||Not Tested
|-
|-
!16
!16
|IRQ_sub_2_slow
|IRQ_sub_2_slow
|
|
|Not Tested ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} test 236 ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} test 236 ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} test 220 ||Not Tested
|-
|-
!colspan="13"|LDM
!colspan="13"|LDM
Line 539: Line 538:
|LDM_ALU_IMM
|LDM_ALU_IMM
|
|
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested ||Not Tested  
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested  
|-
|-
!03
!03
Line 549: Line 548:
|LDM_Bx
|LDM_Bx
|
|
|{{Pass}} ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} (crash) ||{{Fail}} test 1 ||Not Tested ||Not Tested  
|{{Pass}} ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Fail}} (crash) ||{{Fail}} test 1 ||{{Fail}} test 1 ||Not Tested  
|-
|-
!05
!05
|LDM_LD
|LDM_LD
|
|
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested ||Not Tested  
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested  
|-
|-
!06
!06
|LDM_MUL_UL_32
|LDM_MUL_UL_32
|
|
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested ||Not Tested  
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested  
|-
|-
!07
!07
|LDM_MUL_UL_SL
|LDM_MUL_UL_SL
|
|
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested ||Not Tested  
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested  
|-
|-
!08
!08
|LDM_Swap
|LDM_Swap
|
|
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested ||Not Tested  
|{{Pass}} ||{{Fail}} test 2 ||{{Pass}} ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||{{Fail}} test 2 ||Not Tested  
|-
|-
!colspan="13"|PPU
!colspan="13"|PPU
Line 576: Line 575:
|Sprite_Disable_Midline
|Sprite_Disable_Midline
|
|
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||Not Tested ||{{Pass}}
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Pass}}
|-
|-
!02
!02
|Sprite_Disable_on_VRAM_Access
|Sprite_Disable_on_VRAM_Access
|
|
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||Not Tested ||{{Pass}}
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Pass}}
|-
|-
!03
!03
Line 596: Line 595:
|start_up
|start_up
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 32 ||{{Pass}} ||{{Fail}} test 56 ||{{Fail}} test 80 ||{{Fail}} test 92 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 32 ||{{Pass}} ||{{Fail}} test 56 ||{{Fail}} test 80 ||{{Fail}} test 92 ||{{Pass}} ||Not Tested
|-
|-
!06
!06
|start_up_vbl
|start_up_vbl
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 92 ||{{Pass}} ||{{Fail}} test 64 ||{{Fail}} test 96 ||{{Fail}} test 94 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 92 ||{{Pass}} ||{{Fail}} test 64 ||{{Fail}} test 96 ||{{Fail}} test 94 ||{{Pass}} ||Not Tested
|-
|-
!07
!07
|start_up_vbl_irq
|start_up_vbl_irq
|
|
|Not Tested ||{{Fail}} test 49 ||{{Pass}} ||{{Fail}} test 48 ||{{Fail}} test 41 ||{{Fail}} test 41 ||{{Fail}} test 46 ||{{Fail}} test 251 ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 49 ||{{Pass}} ||{{Fail}} test 48 ||{{Fail}} test 41 ||{{Fail}} test 41 ||{{Fail}} test 46 ||{{Fail}} test 251 ||{{Fail}} test 47 ||Not Tested
|-
|-
!08
!08
|start_up_vbl_irq_halt
|start_up_vbl_irq_halt
|
|
|Not Tested ||{{Fail}} test 46 ||{{Pass}} ||{{Fail}} test 46 ||{{Fail}} test 41 ||{{Fail}} test 30 ||{{Fail}} test 46 ||{{Fail}} test 244 ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 46 ||{{Pass}} ||{{Fail}} test 46 ||{{Fail}} test 41 ||{{Fail}} test 30 ||{{Fail}} test 46 ||{{Fail}} test 244 ||{{Fail}} test 43 ||Not Tested
|-
|-
!colspan="13"|Prefetcher
!colspan="13"|Prefetcher
Line 623: Line 622:
|prefetcher_boundary_1
|prefetcher_boundary_1
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 81 ||{{Fail}} test 78 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 81 ||{{Fail}} test 78 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 81 ||Not Tested
|-
|-
!03
!03
|prefetcher_boundary_2
|prefetcher_boundary_2
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 78 ||{{Pass}} ||{{Fail}} test 83 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 78 ||{{Pass}} ||{{Fail}} test 83 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!04
!04
|prefetcher_boundary_3
|prefetcher_boundary_3
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 83 ||{{Fail}} test 78 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 83 ||{{Fail}} test 78 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 83 ||Not Tested
|-
|-
!05
!05
|prefetcher_boundary_4
|prefetcher_boundary_4
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 78 ||{{Pass}} ||{{Fail}} test 85 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 78 ||{{Pass}} ||{{Fail}} test 85 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!06
!06
Line 663: Line 662:
|Branch_THUMB_5
|Branch_THUMB_5
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 63 ||{{Fail}} test 51 ||{{Pass}} ||{{Fail}} test 63 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 63 ||{{Fail}} test 51 ||{{Pass}} ||{{Fail}} test 63 ||{{Pass}} ||{{Fail}} test 63 ||Not Tested
|-
|-
!11
!11
|Branch_THUMB_6
|Branch_THUMB_6
|
|
|Not Tested ||{{Fail}} test 181 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 181 ||{{Fail}} test 194 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 181 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 181 ||{{Fail}} test 194 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!12
!12
Line 678: Line 677:
|branch_thumb_arm_3
|branch_thumb_arm_3
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} test 102 ||{{Fail}} (crash) ||{{Pass}} ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} test 102 ||{{Fail}} (crash) ||{{Pass}} ||{{Fail}} test 78 ||Not Tested
|-
|-
!14
!14
|branch_thumb_arm_4
|branch_thumb_arm_4
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 38 ||{{Pass}} ||{{Fail}} test 45 ||{{Pass}} ||Not Tested ||Not Tested
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 38 ||{{Pass}} ||{{Fail}} test 45 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!15
!15
Line 698: Line 697:
|Full_ARM_2
|Full_ARM_2
|
|
|Not Tested ||{{Fail}} test 104 ||{{Pass}} ||{{Fail}} test 105 ||{{Fail}} test 75 ||{{Fail}} test 105 ||{{Fail}} test 125 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 104 ||{{Pass}} ||{{Fail}} test 105 ||{{Fail}} test 75 ||{{Fail}} test 105 ||{{Fail}} test 125 ||{{Pass}} ||{{Fail}} test 104 ||Not Tested
|-
|-
!18
!18
Line 710: Line 709:
|PSR
|PSR
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} (crash) ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}}
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} (crash) ||{{Fail}} test 1 ||{{Fail}} test 249 ||{{Pass}}
|-
|-
!colspan="13"|STM
!colspan="13"|STM
Line 717: Line 716:
|STM_ALU_IMM
|STM_ALU_IMM
|
|
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested ||Not Tested  
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested  
|-
|-
!colspan="13"|THUMB
!colspan="13"|THUMB
Line 724: Line 723:
|blx
|blx
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} (stuck) ||{{Pass}} ||{{Pass}} ||{{Fail}} (stuck) ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} (stuck) ||{{Pass}} ||{{Pass}} ||{{Fail}} (stuck) ||{{Fail}} test 1 ||Not Tested
|-
|-
!02
!02
|cpy
|cpy
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!03
!03
|Pop_no_regs
|Pop_no_regs
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 1 ||{{Pass}} ||Not Tested
|-
|-
!04
!04
|Push_no_regs
|Push_no_regs
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 11 ||{{Pass}} ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 11 ||{{Pass}} ||{{Pass}} ||Not Tested
|-
|-
!colspan="13"|Timer
!colspan="13"|Timer
Line 763: Line 762:
|cpy_data_bios
|cpy_data_bios
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 157 ||{{Pass}} ||{{Fail}} test 172 ||{{Fail}} test 242 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 157 ||{{Pass}} ||{{Fail}} test 172 ||{{Fail}} test 242 ||{{Pass}} ||Not Tested
|-
|-
!02
!02
|dma_from_bios
|dma_from_bios
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 10 ||{{Fail}} test 12 ||{{Pass}} ||{{Fail}} test 14 ||{{Fail}} test 14 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 10 ||{{Fail}} test 12 ||{{Pass}} ||{{Fail}} test 14 ||{{Fail}} test 14 ||{{Fail}} test 6 ||Not Tested
|-
|-
!03
!03
|dma_long
|dma_long
|
|
|Not Tested ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 1 ||{{Pass}} ||{{Fail}} test 1 ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Pass}} ||Not Tested
|-
|-
!04
!04
|prefetch_enable
|prefetch_enable
|
|
|Not Tested ||{{Fail}} test 187 ||{{Pass}} ||{{Fail}} test 175 ||{{Fail}} test 196 ||{{Fail}} test 187 ||{{Pass}} ||{{Fail}} test 37 ||Not Tested ||Not Tested
|Not Tested ||{{Fail}} test 187 ||{{Pass}} ||{{Fail}} test 175 ||{{Fail}} test 196 ||{{Fail}} test 187 ||{{Pass}} ||{{Fail}} test 37 ||{{Fail}} test 191 ||Not Tested
|-
|-
!05
!05
|prefetch_enable_2
|prefetch_enable_2
|
|
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 175 ||{{Fail}} test 199 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 37 ||Not Tested ||Not Tested
|Not Tested ||{{Pass}} ||{{Pass}} ||{{Fail}} test 175 ||{{Fail}} test 199 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 37 ||{{Fail}} test 191 ||Not Tested
|-
|-
|}
|}
Line 813: Line 812:
|arm
|arm
|
|
|{{Fail}} test 365 ||{{Fail}} test 256 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 522 ||{{Pass}} ||{{Fail}} (crash) ||{{Fail}} test 225 ||Not Tested ||Not Tested
|{{Fail}} test 365 ||{{Fail}} test 256 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 522 ||{{Pass}} ||{{Fail}} (crash) ||{{Fail}} test 225 ||{{Pass}} ||Not Tested
|-
|-
!02
!02
|branches
|branches
|
|
|{{Fail}} test 60 ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} (stuck) ||Not Tested ||Not Tested
|{{Fail}} test 60 ||{{Fail}} (stuck) ||{{Pass}} ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||Not Tested
|-
|-
!03
!03
|data_swap
|data_swap
|
|
|{{Fail}} test 455 ||{{Fail}} test 456 ||{{Pass}} ||{{Fail}} (stuck) ||{{Fail}} test 454 ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} test 454 ||Not Tested ||Not Tested
|{{Fail}} test 455 ||{{Fail}} test 456 ||{{Pass}} ||{{Fail}} (stuck) ||{{Fail}} test 454 ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} test 454 ||{{Fail}} test 454 ||Not Tested
|-
|-
!04
!04
|halfword_transfer
|halfword_transfer
|
|
|{{Fail}} test 416 ||{{Fail}} test 256 ||{{Pass}} ||{{Fail}} test 414 ||{{Fail}} test 416 ||{{Fail}} (stuck) ||{{Fail}} test 410 ||{{Fail}} test 410 ||Not Tested ||Not Tested
|{{Fail}} test 416 ||{{Fail}} test 256 ||{{Pass}} ||{{Fail}} test 414 ||{{Fail}} test 416 ||{{Fail}} (stuck) ||{{Fail}} test 410 ||{{Fail}} test 410 ||{{Fail}} test 416 ||Not Tested
|-
|-
!05
!05
|multiply
|multiply
|
|
|{{Fail}} (stuck) ||{{Fail}} test 322 ||{{Pass}} ||{{Fail}} test 320 ||{{Fail}} test 322 ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} (stuck) ||Not Tested ||Not Tested
|{{Fail}} (stuck) ||{{Fail}} test 322 ||{{Pass}} ||{{Fail}} test 320 ||{{Fail}} test 322 ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} (stuck) ||{{Fail}} test 329 ||Not Tested
|-
|-
!colspan="13"|PSR
!colspan="13"|PSR
Line 840: Line 839:
|PSR2
|PSR2
|
|
|{{Fail}} test 8 ||{{Fail}} test 1 ||{{Fail}} test 8 ||{{Fail}} test 1 ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} test 8 ||Not Tested ||Not Tested
|{{Fail}} test 8 ||{{Fail}} test 1 ||{{Fail}} test 8 ||{{Fail}} test 1 ||{{Fail}} (stuck) ||{{Fail}} (stuck) ||{{Fail}} (crash) ||{{Fail}} test 8 ||{{Fail}} test 8 ||Not Tested
|-
|-
!colspan="13"|Timer
!colspan="13"|Timer
Line 847: Line 846:
|Timer_check_count_up_presence
|Timer_check_count_up_presence
|
|
|{{Fail}} test 1 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 4 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 4 ||Not Tested ||Not Tested
|{{Fail}} test 1 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 1 ||{{Fail}} test 4 ||{{Pass}} ||{{Pass}} ||{{Fail}} test 4 ||{{Fail}} test 4 ||Not Tested
|-
|-
|}
|}
Line 1,100: Line 1,099:
!colspan="12"|CiroteMark
!colspan="12"|CiroteMark
|-
|-
![https://cirote3.itch.io/cirote3 Absolute error in ticks]
![https://cirote3.itch.io/cirote3 Difference in ticks]
|1
|1
|{{Pass}} ||{{Fail}} (-267272) ||{{Pass}} ||{{Fail}} (497529) ||{{Fail}} (-6730908) ||{{Fail}} (-262865) ||{{Fail}} (-17908481) ||{{Fail}} (6567849) ||{{Fail}} (231264) ||{{Fail}} (29102)
|{{Pass}} ||{{Fail}} (-267272) ||{{Pass}} ||{{Fail}} (497529) ||{{Fail}} (-6730908) ||{{Fail}} (-262865) ||{{Fail}} (-17908481) ||{{Fail}} (6567849) ||{{Fail}} (-232592) ||{{Fail}} (29102)
|-
|-
!colspan="12"|CasualPokePlayer
!colspan="12"|CasualPokePlayer
Line 1,108: Line 1,107:
![https://github.com/CasualPokePlayer/gba-rtc-test/ GBA RTC Test]
![https://github.com/CasualPokePlayer/gba-rtc-test/ GBA RTC Test]
|17
|17
|{{Fail}} (3) ||{{Fail}} (7) ||{{Fail}} (15) ||{{Fail}} (0) ||{{Fail}} (15) ||{{Fail}} (0) ||{{Fail}} (1) ||{{Fail}} (1) ||Not Tested ||Not Tested  
|{{Fail}} (3) ||{{Fail}} (7) ||{{Fail}} (15) ||{{Fail}} (0) ||{{Fail}} (15) ||{{Fail}} (0) ||{{Fail}} (1) ||{{Fail}} (1) ||{{Fail}} (1) ||Not Tested  
|-
|-
|}
|}

Revision as of 20:05, 26 June 2025

This page documents the results of various emulators and hardware using test ROMs. Emulators are tested using the official BIOS. The number next to the fail state is usually the number of tests passed, so higher equals better. Tests for cartridge features like RTC can be undetected in emulators using hash databases.

Emulator versions tested

Table of emulators
Emulator Version
GBAHawk 2.3.0
NanoBoyAdvance v1.8.2
Mesen commit 93f1da5
SkyEmu v3
mGBA commit e5eeb70
Ares 144
No$GBA 3.06
Visual Boy Advance M 2.1.11
MiSTer_GBA v250621
Analogue Pocket pocket_firmware_1_1.bin 2023-05-04

Tests

gba-suite

gba-suite r88
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket
01 Memory tests 1552 Pass Pass Pass Pass Pass Pass Fail (1394) Fail (1426) Pass Fail (1368)*
02 I/O read tests 130 Pass Pass Pass Pass Fail (128) Pass Fail (129) Fail (100) Fail (129) Pass*
03 Timing tests 2020 Pass Pass Pass Pass Fail (1768) Pass Fail (1233)** Fail (898) Fail (1796) Pass*
04 Timer count-up tests 936 Pass Pass Pass Fail (720)** Fail (744) Fail (921)** Fail (172) Fail (440) Fail (442) Fail (920)*
05 Timer IRQ tests 90 Pass Pass Pass Pass Fail (70) Pass Fail (44) Fail (8) Fail (65) Pass*
06 Shifter tests 140 Pass Pass Pass Pass Pass Pass Pass Fail (132) Pass Pass*
07 Carry tests 93 Pass Pass Pass Pass Pass Pass Pass Pass Pass Pass*
08 Multiply long tests 72 Pass Pass Pass Fail (52) Fail (52) Fail (52) Fail (52) Fail (52) Fail (52) Fail (52)*
09 BIOS math tests 615 Pass Pass Pass Pass Pass Pass Pass Pass Pass Fail (520)*
10 DMA tests 1256 Pass Pass Pass Pass Fail (1232) Pass Fail (1060) Fail (1068) Fail (1248) Fail (1184)*
11 SIO register R/W tests 90 Fail (25) Fail (18) Fail (28) Fail (25) Fail (61) Fail (34) Fail (36) Fail (13) Fail (27) Not Tested
12 SIO timing tests 8 Fail (0) Fail (0) Fail (0) Fail (0) Fail (0) Fail (0) Fail (0) Fail (0) Fail (0) Not Tested
13 Misc. edge case tests*** 10 Fail (8) Fail (8) Fail (8) Fail (4) Fail (8) Fail (7)** Fail (6) Fail (8) Fail (6)** Pass*
14 Video tests 7 Pass Fail (6) Pass Fail (5) Fail (4) Fail (5) Fail (3) Fail (4) Fail (4) Pass*

* tested on r83
** inconsistent results, showcasing highest value seen
*** two of the tests are acting a bit weird and need to be checked, using a flashcart they don't pass

AGS Aging Cartridge

AGS Aging Cartridge v10.0
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket
01 Memory 9 Pass Pass Pass Pass Fail (8) Pass Fail (8) Fail (1) Pass Pass
02 LCD 7 Pass Pass Pass Pass Pass Pass Pass Fail (6) Pass Pass
03 Timer 3 Pass Pass Pass Pass Pass Pass Fail (2) Fail (2) Pass Pass
04 DMA 9 Pass Pass Pass Pass Pass Pass Fail (8) Fail (7) Pass Pass
05 COM N/A Skip Skip Skip Skip Skip Skip Skip Skip Skip Skip
06 Key Input 1 Pass Pass Pass Pass Pass Pass Pass Pass Pass Pass
07 Interrupt 7 Pass Pass Pass Pass Pass Fail (4) Fail (6) Fail (5) Pass Pass

gba-tests (jsmolka)

jsmolka gba-tests commit 49204e1
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket
01 arm Pass Pass Pass Pass Fail test 522 Pass Fail (crash) Fail test 225 Pass Pass*
02 bios Pass Pass Pass Pass Pass Pass Fail test 3 Fail test 1 Pass Pass
03 memory Pass Pass Pass Pass Pass Pass Pass Pass Pass Pass
04 nes Pass Pass Pass Pass Pass Pass Fail test 1 Pass Pass Pass
05 thumb Pass Pass Pass Pass Fail test 230 Pass Fail test 225 Fail test 221 Pass Pass
Save
01 none Pass Pass Pass Pass Pass Pass Pass Pass Fail test 1 Not Tested
02 sram Pass Pass Pass Pass Pass Pass Pass Fail test 6 Fail test 1 Pass
03 flash64** Fail test 2 Pass Pass Pass Fail test 10 Pass Fail test 10 Fail test 6 Fail test 1 Pass
04 flash128** Fail test 2 Pass Pass Pass*** Fail test 10 Pass Fail test 10 Fail test 6 Fail test 1 Pass

* tested on commit a6447c5
** these tests fail on a real development flash board and probably are testing conformity with the flash implementation of modern flashcarts
*** fails on test 9 on reruning the test after the first time

gba-tests (alyosha)

alyosha gba-tests commit f57774d
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket*
DMA
01 DMA_Mode_Change Not Tested Pass Pass Fail test 45 Pass Pass Pass Pass Pass Not Tested
02 DMA_pause_timing_end_1 Not Tested Pass Pass Fail test 216 Fail test 6 Fail test 243 Fail test 12 Pass Pass Not Tested
03 DMA_pause_timing_end_2 Not Tested Pass Pass Fail test 217 Fail test 5 Fail test 244 Pass Fail test 1 Fail test 10 Not Tested
04 DMA_pause_timing_end_3 Not Tested Pass Pass Fail test 216 Fail test 6 Fail test 243 Fail test 12 Pass Fail test 11 Not Tested
05 DMA_pause_timing_end_4 Not Tested Fail test 14 Pass Fail test 217 Fail test 5 Fail test 244 Fail test 12 Fail test 1 Fail test 8 Not Tested
06 DMA_pause_timing_mid_1 Not Tested Pass Pass Fail test 217 Fail test 6 Fail test 244 Fail test 12 Pass Pass Not Tested
07 DMA_pause_timing_mid_2 Not Tested Pass Pass Fail test 216 Fail test 5 Fail test 245 Fail test 12 Fail test 1 Fail test 8 Not Tested
08 DMA_pause_timing_ROM_to_IWRAM Not Tested Pass Pass Fail test 113 Fail test 112 Fail test 117 Fail test 109 Fail test 9 Fail test 111 Not Tested
09 DMA_ROM_Fixed Pass Fail test 242 Pass Fail test 240 Fail test 242 Pass Fail test 240 Fail test 9 Fail test 240 Pass
FIFO
01 FIFO Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2
02 FIFO_2 Pass Fail test 80 Pass Fail test 51 Fail test 51 Fail test 51 Fail test 54 Fail test 46 Fail test 51 Fail test 80
03 FIFO_3 Not Tested Fail test 174 Pass Fail test 102 Fail test 111 Fail test 146 Fail test 121 Fail test 75 Fail test 51 Not Tested
04 FIFO_4 Not Tested Fail test 124 Pass Fail test 95 Fail test 95 Fail test 95 Fail test 94 Fail test 45 Fail test 95 Not Tested
05 FIFO_5 Not Tested Pass Pass Fail test 59 Fail test 59 Fail test 59 Fail test 62 Fail test 54 Fail test 59 Not Tested
06 FIFO_6 Not Tested Fail test 118 Pass Fail (stuck) Pass Fail test 117 Fail test 90 Pass Pass Not Tested
Interactions
01 Halt_DMA_IRQ Pass Fail test 184 Pass Fail test 184 Fail test 184 Fail test 184 Fail test 184 Fail test 184 Fail test 184 Not Tested
02 Halt_DMA_IRQ_Read_OAM Pass Fail test 184 Pass Fail test 184 Fail test 184 Fail test 184 Fail test 56 Fail test 184 Fail test 184 Not Tested
03 Halt_IRQ Pass Fail test 184 Pass Fail test 184 Fail test 184 Fail test 94 Fail test 184 Fail test 184 Fail test 184 Not Tested
04 Internal_Cycle_DMA_IRQ Pass Fail test 6 Pass Fail test 248 Fail test 4 Fail test 248 Fail test 8 Fail test 54 Fail test 6 Fail test 8
05 Internal_Cycle_DMA_IRQ_7 Pass Fail test 6 Pass Fail test 248 Fail test 4 Fail test 248 Fail test 6 Fail test 10 Fail test 6 Not Tested
06 Internal_Cycle_DMA_IRQ_br Pass Fail test 20 Pass Pass Fail test 20 Fail test 20 Pass Fail test 76 Fail test 24 Not Tested
07 Internal_Cycle_DMA_IRQ_br1_IWRAM Pass Pass Pass Pass Pass Pass Fail test 90 Fail test 90 Fail test 36 Not Tested
08 Internal_Cycle_DMA_IRQ_Br_pre Pass Pass Pass Fail test 28 Fail test 26 Pass Pass Fail test 76 Pass Not Tested
09 Internal_Cycle_DMA_IRQ_Br_pre_tim Pass Pass Pass Fail test 32 Fail test 27 Fail test 255 Fail test 2 Fail test 1 Fail test 25 Not Tested
10 Internal_Cycle_DMA_IRQ_ldr_IWRAM Pass Fail test 32 Pass Fail test 16 Fail test 20 Fail test 20 Fail test 32 Fail test 38 Fail test 28 Not Tested
11 Internal_Cycle_DMA_IRQ_nop_IWRAM Pass Pass Pass Fail test 36 Pass Pass Fail test 94 Fail test 94 Pass Not Tested
12 Internal_Cycle_DMA_IRQ_ST Pass Fail test 8 Pass Fail test 248 Fail test 4 Fail test 248 Pass Fail test 54 Fail test 6 Not Tested
13 Internal_Cycle_DMA_IRQ_ST_p3 Pass Fail test 8 Pass Fail test 6 Fail test 6 Fail test 8 Pass Fail test 62 Pass Not Tested
14 Internal_Cycle_DMA_Mul Pass Pass Pass Fail test 40 Fail test 41 Fail test 43 Fail test 37 Pass Fail test 41 Pass
15 Internal_Cycle_DMA_MUL_IRQ Pass Pass Pass Fail test 8 Fail test 14 Fail test 6 Fail test 134 Fail test 24 Fail test 20 Not Tested
16 Internal_Cycle_DMA_TIM_Br_pre Pass Pass Pass Fail test 32 Fail test 27 Fail test 255 Fail test 2 Fail test 1 Fail test 25 Not Tested
IRQ
01 BL_1 Not Tested Pass Pass Pass Pass Pass Fail (crash) Pass Pass Not Tested
02 BL_IRQ Not Tested Pass Pass Fail test 245 Fail test 240 Pass Fail test 245 Fail test 224 Fail test 250 Not Tested
03 BL_IRQ_2 Not Tested Pass Pass Fail test 2 Fail test 2 Pass Fail (crash) Fail test 2 Fail test 2 Not Tested
04 BL_IRQ_3 Not Tested Pass Pass Fail test 1 Fail test 1 Pass Fail test 1 Fail test 1 Fail test 1 Not Tested
05 BL_IRQ_R14 Not Tested Pass Pass Pass Fail test 1 Pass Fail test 1 Fail test 1 Fail test 1 Not Tested
06 Halt_PC Pass Fail test 212 Pass Fail test 1 Fail test 1 Fail test 1 Fail test 1 Fail test 1 Fail test 2 Pass
07 Halt_PC_2 Pass Pass Pass Fail test 239 Fail test 235 Pass Fail test 238 Fail test 222 Fail test 242 Fail test 239
08 Halt_PC_3 Pass Fail test 237 Pass Fail test 237 Fail test 232 Pass Fail test 238 Fail test 220 Fail test 239 Fail test 239
09 Halt_PC_4 Pass Pass Pass Fail test 242 Fail test 236 Pass Fail test 240 Fail test 224 Fail test 245 Fail test 242
10 IE Pass Pass Pass Fail test 3 Fail test 3 Pass Pass Fail test 4 Fail test 2 Pass
11 IF Pass Pass Pass Fail test 3 Fail test 3 Pass Fail test 6 Fail test 2 Fail test 2 Pass
12 IF_Timer Pass Pass Pass Fail test 2 Fail test 2 Pass Fail test 2 Fail test 1 Fail test 2 Pass
13 IRQ_sub Pass Pass Pass Fail test 240 Fail test 247 Pass Fail test 251 Fail test 224 Fail test 245 Pass
14 IRQ_sub_slow Not Tested Pass Pass Fail test 229 Fail test 239 Pass Fail test 243 Fail test 224 Fail test 237 Not Tested
15 IRQ_sub_2 Not Tested Pass Pass Fail test 28 Fail test 218 Fail (stuck) Fail (stuck) Fail test 216 Fail test 220 Not Tested
16 IRQ_sub_2_slow Not Tested Fail (stuck) Pass Fail test 236 Fail (stuck) Fail (stuck) Fail (stuck) Fail (stuck) Fail test 220 Not Tested
LDM
01 LDM_ALU Pass Fail test 2 Pass Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 9
02 LDM_ALU_IMM Pass Fail test 2 Pass Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Not Tested
03 LDM_ALU_Store Pass Fail test 6 Pass Fail test 6 Fail test 6 Fail test 6 Fail test 6 Fail test 6 Fail test 6 Pass
04 LDM_Bx Pass Fail test 1 Pass Fail test 1 Fail test 1 Fail test 1 Fail (crash) Fail test 1 Fail test 1 Not Tested
05 LDM_LD Pass Fail test 2 Pass Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Not Tested
06 LDM_MUL_UL_32 Pass Fail test 2 Pass Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Not Tested
07 LDM_MUL_UL_SL Pass Fail test 2 Pass Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Not Tested
08 LDM_Swap Pass Fail test 2 Pass Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Fail test 2 Not Tested
PPU
01 Sprite_Disable_Midline Pass Fail Pass Fail Fail Fail Fail Fail Fail Pass
02 Sprite_Disable_on_VRAM_Access Pass Fail Pass Fail Fail Fail Fail Fail Fail Pass
03 Sprite_Last_VRAM_Access Pass Pass Pass Fail test 141 Fail test 143 Fail test 173 Fail test 155 Fail test 116 Fail test 141 Pass
04 Sprite_Last_VRAM_Access_Free Pass Fail test 121 Pass Fail test 119 Fail test 121 Fail test 119 Fail test 119 Fail test 9 Fail test 119 Pass
05 start_up Not Tested Pass Pass Fail test 32 Pass Fail test 56 Fail test 80 Fail test 92 Pass Not Tested
06 start_up_vbl Not Tested Pass Pass Fail test 92 Pass Fail test 64 Fail test 96 Fail test 94 Pass Not Tested
07 start_up_vbl_irq Not Tested Fail test 49 Pass Fail test 48 Fail test 41 Fail test 41 Fail test 46 Fail test 251 Fail test 47 Not Tested
08 start_up_vbl_irq_halt Not Tested Fail test 46 Pass Fail test 46 Fail test 41 Fail test 30 Fail test 46 Fail test 244 Fail test 43 Not Tested
Prefetcher
01 boundary_test_1 Pass Fail test 33 Pass Fail test 33 Fail test 27 Fail test 33 Fail test 39 Pass Fail test 34 Pass
02 prefetcher_boundary_1 Not Tested Pass Pass Fail test 81 Fail test 78 Pass Pass Pass Fail test 81 Not Tested
03 prefetcher_boundary_2 Not Tested Pass Pass Pass Fail test 78 Pass Fail test 83 Pass Pass Not Tested
04 prefetcher_boundary_3 Not Tested Pass Pass Fail test 83 Fail test 78 Pass Pass Pass Fail test 83 Not Tested
05 prefetcher_boundary_4 Not Tested Pass Pass Pass Fail test 78 Pass Fail test 85 Pass Pass Not Tested
06 branch_THUMB Pass Pass Pass Fail test 40 Fail test 29 Pass Fail test 37 Pass Fail test 40 Pass
07 Branch_THUMB_2 Pass Fail test 19 Pass Fail test 13 Fail test 33 Fail test 19 Fail test 45 Pass Fail test 45 Pass
08 Branch_THUMB_3 Pass Fail test 45 Pass Fail test 36 Fail test 35 Fail test 45 Fail test 41 Pass Fail test 36 Pass
09 Branch_THUMB_4 Pass Fail test 55 Pass Fail test 27 Fail test 28 Fail test 63 Fail test 27 Pass Fail test 27 Pass
10 Branch_THUMB_5 Not Tested Pass Pass Fail test 63 Fail test 51 Pass Fail test 63 Pass Fail test 63 Not Tested
11 Branch_THUMB_6 Not Tested Fail test 181 Pass Pass Pass Fail test 181 Fail test 194 Pass Pass Not Tested
12 Branch_THUMB_ARM Pass Fail test 57 Pass Fail test 59 Fail test 49 Pass Fail test 65 Pass Fail test 59 Pass
13 branch_thumb_arm_3 Pass Pass Pass Fail (stuck) Pass Fail test 102 Fail (crash) Pass Fail test 78 Not Tested
14 branch_thumb_arm_4 Pass Pass Pass Pass Fail test 38 Pass Fail test 45 Pass Pass Not Tested
15 DMA Pass Pass Pass Fail test 50 Fail test 40 Fail test 45 Fail test 66 Pass Fail test 59 Pass
16 Full_ARM Pass Fail test 51 Pass Fail test 1 Fail test 1 Fail test 1 Fail test 1 Fail test 1 Fail test 1 Pass
17 Full_ARM_2 Not Tested Fail test 104 Pass Fail test 105 Fail test 75 Fail test 105 Fail test 125 Pass Fail test 104 Not Tested
18 Full_THUMB Pass Pass Pass Fail test 36 Fail test 31 Pass Fail test 49 Pass Fail test 44 Pass
PSR
01 PSR Pass Pass Pass Fail test 1 Fail test 1 Pass Fail (crash) Fail test 1 Fail test 249 Pass
STM
01 STM_ALU_IMM Pass Pass Pass Pass Pass Pass Pass Pass Pass Not Tested
THUMB
01 blx Not Tested Pass Pass Pass Fail (stuck) Pass Pass Fail (stuck) Fail test 1 Not Tested
02 cpy Not Tested Pass Pass Pass Pass Pass Pass Pass Pass Not Tested
03 Pop_no_regs Not Tested Pass Pass Fail test 1 Fail test 1 Pass Fail test 1 Fail test 1 Pass Not Tested
04 Push_no_regs Not Tested Pass Pass Pass Pass Pass Fail test 11 Pass Pass Not Tested
Timer
01 Timer Pass Fail test 1 Pass Fail test 3 Fail test 1 Fail test 3 Fail test 3 Fail test 3 Fail test 3 Fail test 3
02 Timer_disable Pass Pass Pass Fail test 254 Fail test 251 Pass Fail test 244 Fail test 237 Fail test 254 Pass
03 Timer_reset Fail test 1 Fail test 2 Pass Fail test 1 Fail test 1 Fail test 1 Fail test 1 Fail test 1 Fail test 1 Pass
Timing
01 cpy_data_bios Not Tested Pass Pass Pass Fail test 157 Pass Fail test 172 Fail test 242 Pass Not Tested
02 dma_from_bios Not Tested Pass Pass Fail test 10 Fail test 12 Pass Fail test 14 Fail test 14 Fail test 6 Not Tested
03 dma_long Not Tested Fail test 1 Pass Fail test 1 Pass Pass Pass Fail test 1 Pass Not Tested
04 prefetch_enable Not Tested Fail test 187 Pass Fail test 175 Fail test 196 Fail test 187 Pass Fail test 37 Fail test 191 Not Tested
05 prefetch_enable_2 Not Tested Pass Pass Fail test 175 Fail test 199 Pass Pass Fail test 37 Fail test 191 Not Tested

* tested with openFPGA spiritualized1997 core

gba-tests (png183)

png183 gba-tests commit ae185b2
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket
ARM
01 arm Fail test 365 Fail test 256 Pass Pass Fail test 522 Pass Fail (crash) Fail test 225 Pass Not Tested
02 branches Fail test 60 Fail (stuck) Pass Fail (stuck) Fail (stuck) Fail (stuck) Fail (crash) Fail (stuck) Fail (stuck) Not Tested
03 data_swap Fail test 455 Fail test 456 Pass Fail (stuck) Fail test 454 Fail (stuck) Fail (crash) Fail test 454 Fail test 454 Not Tested
04 halfword_transfer Fail test 416 Fail test 256 Pass Fail test 414 Fail test 416 Fail (stuck) Fail test 410 Fail test 410 Fail test 416 Not Tested
05 multiply Fail (stuck) Fail test 322 Pass Fail test 320 Fail test 322 Fail (stuck) Fail (crash) Fail (stuck) Fail test 329 Not Tested
PSR
01 PSR2 Fail test 8 Fail test 1 Fail test 8 Fail test 1 Fail (stuck) Fail (stuck) Fail (crash) Fail test 8 Fail test 8 Not Tested
Timer
01 Timer_check_count_up_presence Fail test 1 Pass Pass Fail test 1 Fail test 4 Pass Pass Fail test 4 Fail test 4 Not Tested

NBA hw-test

NBA hw-test commit 4571fc5
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket
Bus
01 128kb-boundary 12 Pass Fail (9) Pass Fail (0) Fail (6) Pass Fail (7) Fail (0) Fail (6) Fail (stuck)*
DMA
01 burst-into-tears 3 Pass Fail (0) Pass Fail (0) Fail (1) Pass Fail (1) Fail (0) Fail (1) Fail (1)
02 force-nseq-access 2 Pass Pass Pass Fail (0) Fail (0) Pass Fail (0) Fail (0) Fail (0) Pass
03 latch 3 Pass Pass Pass Pass Fail (1) Pass Fail (0) Fail (1) Fail (1) Pass
04 start-delay 1 Pass Pass Pass Fail Fail Pass Fail Fail Fail Pass
IRQ
01 irq-delay 3 Pass Pass Pass Fail (0) Fail (1) Pass Fail (0) Fail (1) Fail (0) Pass
PPU
01 bgpd 1 Pass Pass Pass Fail Fail Fail Fail Fail Fail Pass
02 bgx 1 Pass Pass Pass Fail Fail Fail Fail Fail Fail Pass
03 dispcnt-latch 1 Pass Pass Pass Fail Fail Pass Fail Fail Fail Pass
04 greenswap 1 Pass Pass Pass Fail Fail Fail Fail Fail Fail Fail
05 sprite-hmosaic 4 Pass Pass Pass Fail Fail Pass Fail Fail Fail Not tested
06 status-irq-dma 4 Pass Pass Pass Fail (0) Fail (0) Pass Fail (stuck) Fail (stuck) Fail (0) Pass
07 vram-mirror 10 Pass Pass Pass Fail (6) Pass Pass Fail (7) Pass Fail (8) Fail (7)
Timer
01 reload 7 Pass Pass Pass Fail (5) Fail (4) Pass Fail (0) Fail (2) Fail (4) Pass
02 start-stop 2 Pass Pass Pass Fail (1) Fail (1) Pass Pass Fail (1) Fail (1) Pass
Misc
01 halt-cnt 6 Pass Fail (5) Pass Fail (2) Fail (2) Fail (3) Fail (1) Fail (stuck) Fail (stuck) Fail (2)

* tested on commit 40355cb

Hades Tests

Hades-Tests commit 25ec4b4
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket*
01 bios-openbus 12 Pass Pass Pass Pass Pass Pass Pass Fail (0) Pass Pass
02 dma-latch** 4 Fail (3) Fail (3) Fail (3) Pass Fail (1) Fail (3) Fail (0) Fail (0) Fail (1) Fail (3)
03 dma-start-delay 8 Pass Pass Pass Fail (0) Fail (0) Fail (6) Fail (0) Fail (0) Fail (0) Pass
04 timer-basic 10 Pass Pass Pass Fail (2) Fail (2) Pass Pass Fail (6) Fail (2) Pass

* tested with openFPGA spiritualized1997 core
** fourth test is acting a bit weird and needs to be checked, using a flashcart it doesn't pass

AGBEEG Aging Cartridge

AGBEEG Aging v0.0.2
No. Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket
01 Cartridge 2 Pass Pass Pass Fail (1) Fail (0) Fail (1) Fail (0) Fail (0) Fail (0) Fail (1)
02 CPU 3 Pass Pass Pass Fail (1) Fail (1) Pass Fail (2) Fail (2) Fail (1) Fail (2)
03 DMA 1 Pass Pass Pass Fail Fail Fail Fail Fail Fail Pass

Other tests

Other tests
Test Name Subtests GBAHawk
 NanoBoyAdvance
 Mesen
 SkyEmu
 mGBA
 ares
 No$GBA
 Visual Boy Advance M
 MiSTer_GBA
 Analogue Pocket
GValiente
Background palette h-blank update - circle 1 Pass Pass Pass Pass Pass Pass Pass Pass Pass Pass
Sprite update HDMA - diamond 1 Pass Pass Pass Pass Fail Pass Fail Fail Fail Pass
Sprite border HDMA - cube 1 Pass Pass Pass Pass Fail Pass Fail Fail Fail Pass
Max sprites per scanline 1 Pass Pass Pass Fail Pass Fail Fail Pass Fail Pass
Velipso
Large sprite row warp 2 Pass Pass Pass Pass Pass Fail Fail Fail Fail Pass
Interrupt timing vblank + timer0* 1 Pass Pass Pass Fail Fail Fail Fail Fail Fail Fail
Ladystarbreeze
Mid-frame video capture DMA 1 Pass Pass Pass Pass Fail Pass Fail (stuck) Fail (stuck) Fail (stuck) Pass
CiroteMark
Difference in ticks 1 Pass Fail (-267272) Pass Fail (497529) Fail (-6730908) Fail (-262865) Fail (-17908481) Fail (6567849) Fail (-232592) Fail (29102)
CasualPokePlayer
GBA RTC Test 17 Fail (3) Fail (7) Fail (15) Fail (0) Fail (15) Fail (0) Fail (1) Fail (1) Fail (1) Not Tested

* Test is acting a bit weird and needs to be checked, using a flashcart it doesn't pass

Test ROMs

Other Results

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