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this is why
|wave
|{{Fail}} ||{{Fail}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}} ||{{Fail}}
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!colspan="15"|CPU Instrs
|-
!01
|Special
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}}
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!02
|interrupts
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}}
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!03
|op sphl
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}}
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!04
|op r imm
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}}
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!05
|op rp
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}}
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!06
|ld r r
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}}
|-
!07
|jr jp call ret rst
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}}
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!08
|misc instrs
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}}
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!09
|op r r
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}}
|-
!10
|bit ops
|{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}}
|-
!11
|op a(hl)
|{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}} ||{{Pass}} ||{{Pass}} ||{{Fail}} ||{{Pass}}
|}
