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→Subcycle accuracy: Added the simplest example I can think of for differently-clocked components.
Worse than that, as the Z80 tests WAIT only once every machine cycle, not every clock cycle, missing it as a result of sampling at the wrong time can cause a net error of four or more cycles.
Using the broad brush of cycle accuracy can also cause problems in machines with multiple clock signals — component A being accurate only to the complete clock cycle can leave it as observably inaccurate if component B is running with a quicker clock. A simple example of this can be found in the BBC Micro, where the 6522 timer chips run at 1Mhz while the CPU runs at 2Mhz. 6522s generate an interrupt half a cycle after they underflow. Therefore if the 6522s in a BBC Micro are emulated only in whole-cycle steps, they will observably trigger interrupts a cycle late from the point of view of the CPU. In practice this can cause some copy protection mechanisms to fail.
Impinging upon chip accuracy, some chips, such as the Commodore 64's [[wikipedia:MOS_Technology_SID|SID]] are part digital and part analogue. The analogue part can be emulated in a discrete fashion, but it is often desirable to take those discrete steps at a multiple of the clock rate. However the difference is usually not observable to other components in the emulated machine so although this is subcycle accuracy as some part of the state of the chip is known at a precision of greater than one cycle, it doesn't tend to affect the design of the emulator as a whole.
